1.0 Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection circuits and, more particularly, to ESD protection circuits which utilize floating lateral clamp diodes.
2.0 Description of the Related Art
In recent years, increasing attention has been devoted to protecting packaged integrated circuits from damage which results from an electrostatic discharge (ESD) event. This has become increasingly important as the gate oxide thickness of MOS transistors has become thinner due to improved processing technologies which are now commonly in use.
An ESD event typically occurs when the packaged chip is exposed to static electricity, such as when the pins are touched by an ungrounded person handling the chip prior to installation, or when the chip slides across another surface on its pins.
FIGS. 1A and 1B show schematic diagrams which illustrate a portion of a conventional chip 100. As shown in FIGS. 1A and 1B, chip 100 includes a plurality of input/output (I/O) pins, such as first and second I/O pins 110 and 112, each of which is connected to the core of chip 100.
In operation, I/O pins 110 and 112 either receive signals that have been output by an external driver, such as driver 114, or output signals that have been received from an internal driver, such as internal driver 116.
As further shown in FIGS. 1A and 1B, chip 100 also includes a VCC wire 120 and a ground wire 122 which are both formed to completely encircle the periphery of chip 100. In addition, chip 100 further includes an ESD protection circuit which, in turn, includes a plurality of upper clamp diodes, such as diodes D1 and D3, and a plurality of lower clamp diodes, such as diodes D2 and D4.
Each upper clamp diode has an anode connected to an I/O pin, and a cathode connected to VCC wire 120. Similarly, each lower clamp diode has an anode connected to ground wire 122 and a cathode connected to an I/O pin. Furthermore, the ESD protection circuit also includes a plurality of ESD switches, such as ESD switch 130, which are connected to VCC wire 120 and ground wire 122.
As shown in FIG. 1A, when first I/O pin 110 is positively charged with respect to second I/O pin 112 in response to an ESD event, the resulting ESD current Izap flows from pin 110 through diode D1, ESD switch 130, and diode D4 to pin 112.
Similarly, as shown in FIG. 1B, when second I/O pin 112 is positively charged with respect to first I/O pin 110 in response to an ESD event, the resulting current Izap flows from pin 112 through diode D3, ESD switch 130, and diode D2 to pin 110.
In both of the aforementioned cases, the current Izap flows through ESD switch 130 in the same direction. Thus ESD switch 130 is conventionally a unidirectional switch.
FIG. 2 shows one possible embodiment of the ESD switch 130. As shown in FIG. 2, switch 130 includes a switch transistor 210, an inverter 212, and an RC circuit 214. Switch transistor 210 has a drain connected to VCC wire 120, a source connected to ground wire 122, and a gate.
Inverter 212, in turn, includes a p-channel transistor 220 that has a drain connected to the gate of transistor 210, a source connected to VCC wire 120, and a gate; and an n-channel transistor 222 that has a drain connected to the drain of transistor 220, a source connected to ground wire 122, and a gate connected to the gate of transistor 220.
Furthermore, RC circuit 214 includes a resistor R which is connected to the gates of transistors 220 and 222, and to VCC wire 120; and a capacitor C which is connected to resistor R, and to ground wire 122.
In operation, the values for R and C must be chosen such that the RC time constant will be long with respect to an ESD event (approximately 5-25 ns), and short with respect to the power supply rise time (which cannot be faster than 4 ms, assuming a 60 Hz AC line). This restriction will insure that switch transistor 210 will turn on during an ESD event, but will not turn on when the power supply is initially applied.
FIG. 3 shows a schematic diagram which illustrates how the upper and lower clamp diodes D1 and D2 were implemented using the prior art. As shown in FIG. 3, clamp diodes D1 and D2 are made from a pair of parasitic lateral bipolar transistors Q1 and Q2 that are associated with a pair of very large p-channel and n-channel CMOS devices M1 and M2. The bipolar transistors Q1 and Q2 are configured with their bases connected to their collectors in order to form the required upper and lower clamp diodes D1 and D2.
3.0 ESD Diode Requirements
In order to provide adequate ESD protection, clamp diodes D1 and D2 must have a very low forward voltage drop. This implies that diodes D1 and D2 must have a very low forward resistance (approximately 1-2 ohms) since diodes D1 and D2 must conduct a very high forward current (approximately 1.3 A-2.0 A) during an ESD event.
4.0 Disadvantages of the Prior Art
The primary disadvantages of the prior art are discussed below.
4.1 Large Chip Area, High Pin Capacitance and High Input Leakage
In order to meet stringent ESD diode requirements, CMOS transistors M1 and M2 in FIG. 3 must be made very large. This large size, in turn, has three disadvantages. First, large CMOS transistors consume more silicon real estate than smaller CMOS transistors and, therefore, increase the die area required.
Second, large CMOS transistors connected to I/O pins, such as transistors M1 and M2, increase the pin capacitance to approximately 6-12 pF, a significant disadvantage (especially for switchable high-impedance bus pins, such as TRI-STATE™ pins). Third, the large pn junction periphery/area present in large CMOS transistors also increases the input leakage current.
4.2 No ESD Protection For Floating Ground Lines on Mixed Signal Chips
Another serious disadvantage to forming clamp diodes D1 and D2 from parasitic bipolar devices relates to the design of mixed-signal (analog/digital) chips. FIG. 4 shows a schematic diagram which illustrates a portion of a conventional mixed-signal chip 400.
As illustrated by chip 400 in FIG. 4, mixed signal chips usually contain multiple ground lines. These ground lines can be broadly classified as dirty ground lines DGL, clean ground lines CGL, analog ground lines AGL, and substrate ground lines SGL.
Dirty ground lines only service the noisy (high di/dt) digital output buffers. Dirty ground lines are so named because high di/dt output buffers can generate significant ground bounce (switching noise) when multiple output drivers discharge their load capacitances on the same ground line at the same time.
FIG. 5 shows a circuit diagram which illustrates a portion of an output circuit 500. As shown in FIG. 5, output circuit 500 includes a common ground line 510, and a series of output drivers driver#1-driver#N which are each connected to common ground line 510.
During normal operation, when a single output driver is switched from a logic high to a logic low, a time varying discharge current i(t)D is placed on ground line 510. Similarly, when each of the output drivers driver#1-driver#N simultaneously switches from a logic high to a logic low, a large time varying current is placed on ground line 510.
The large time varying current, which is the sum of the individual time varying currents i(t)D, causes the voltage on ground line 510 to also vary due to the inductance of ground line 510 (which is shown as an inductor L). As shown in EQ. 1, the voltage variation VLG on ground line 510 is defined as follows:VLG=L*N(di(t)/dt)  EQ. 1where L represents the inductance of ground wire 510 (including package inductance and bondwire inductance), N represents the number of drivers driver#1-driver#N that are discharged at the same time, and di(t)/dt represents the time varying discharge current i(t)D of a single driver.
Thus, as shown in FIG. 5, an extremely high ground bounce (switching noise) can be generated when several drivers driver#1-driver#N switch from a logic high level to a logic low level at the same time.
Clean ground lines usually service the relatively quiet (low di/dt) internal standard cells and/or digital macro cells. Depending upon the analog signal levels involved, the clean ground lines may or may not be connected to the ground lines which service the analog blocks.
In order to keep substrate noise to an absolute minimum, one or more substrate ground pads can be used. These pads should only be connected to the P-substrate, with as many substrate contacts as possible.
In order to minimize the amount of switching noise which is directly coupled into the substrate, the clean and dirty ground lines must be isolated from the substrate (i.e. not directly connected to it), and they must also be isolated from each other.
Since these on-chip ground lines are effectively floating with respect to the substrate, they cannot be ESD protected using clamp diodes formed from parasitic bipolar devices. The reason for this can be seen by examining FIG. 3.
As shown in the figure, the base of the parasitic NPN transistor Q2 is formed in the P-substrate. Since the base and collector of transistor Q2 must be connected together to form the anode of lower clamp diode D2, the anode of diode D2 must also be connected to the substrate.
This constraint makes it impossible to ESD protect the floating clean and dirty ground lines, since they are not directly connected to the substrate. This lack of ESD protection for the multiple ground lines on mixed signal chips is a major limitation.
4.3 High Forward Voltage Drop
There is another serious disadvantage to forming clamp diodes D1 and D2 from parasitic bipolar transistors—high forward voltage drop across the clamp diodes. The only way to mitigate this problem is to make the P-channel/N-channel CMOS devices (M1/M2 in FIG. 3) extremely large in size. As described above, however, large size wastes valuable chip area, increases pin capacitance (extremely bad for switchable high-impedance outputs, such as TRI-STATES™ outputs) and increases the leakage current at each pin.
The basic reasons for the high diode forward voltage drop can be see by examining the equations which define the voltage drops VD1 and VD2 across diodes D1 and D2 in FIG. 3. As shown by EQ. 2, the forward voltage drop VD1, across upper clamp diode D1, is defined as follows:VD1=VbeQ1+(ICQ1/BQ1) (RBP+RP)  EQ. 2where VbeQ1 is the base-emitter voltage of parasitic transistor Q1, ICQ1 is the forward collector current of parasitic transistor Q1, BQ1 is the beta of parasitic transistor Q1, RBP is the base resistance associated with the resistivity of the N-well, and RP is the base contact resistance due to aluminum/N-well contact.
Similarly, as shown by EQ. 3, the forward voltage drop VD2, across lower clamp diode D2, is defined as follows:VD2=VbeQ2+(ICQ2/BQ2) (RBN+RN)  EQ. 3where VbeQ2 is the base-emitter voltage of parasitic transistor Q2, ICQ2 is the forward collector current of parasitic transistor Q2, BQ2 is the beta of parasitic transistor Q2, RBN is the base resistance associated with the resistivity of the p-substrate, and RN is the base contact resistance due to the aluminum/p-substrate contact.
In the prior art shown in FIG. 3, transistors Q1 and Q2 are implemented as lateral bipolar devices, which are known to have low betas at high collector current. Therefore, because high collector current flows during an ESD event, the betas of Q1 and Q2 will be low, thereby increasing the forward voltage drops VD1 and VD2 in the equivalent ESD protection diodes D1 and D2.
Furthermore, as shown in EQs. 2 and 3, the resistor values RBP and RBN must also be minimized in order to minimize the diode forward voltage drops VD1 and VD2. Since resistor values RBP and RBN are respectively associated with columns of N-well contacts and substrate contacts, the best way to minimize the resistance values of RBP and RBN would be to place the N-well contacts and substrate contacts directly on top of the bases of parasitic transistors Q1 and Q2. This cannot be done, however, because the bases are covered by the poly gates associated with MOS transistors M1 and M2. Thus, it is very difficult to make the resistance values RBP and RBN very low in value. The best that can be done is to place the associated N-well/substrate contacts as close as possible to the gates of MOS transistors M1 and M2. Increasing the number of N-well/substrate contact columns also helps, but significantly increases the area required to build the ESD protection diodes D1 and D2.
4.4 No ESD Protection For Multiple VCC Lines on Mixed Signal Chips
Another disadvantage of the ESD protection circuit shown in FIG. 3 is that it does not provide any means for ESD protecting the multiple, isolated VCC lines which are usually found on mixed-signal chips. FIG. 6 shows a schematic diagram which illustrates a conventional mixed-signal chip 600.
As illustrated by chip 600 in FIG. 6, these lines can be broadly classified as dirty VCC lines DVL, clean VCC lines CVL, and analog VCC lines AVL. Dirty VCC lines only service the noisy (high di/dt) digital output buffers because, as with the dirty ground lines, high di/dt buffers can generate significant VCC bounce (switching noise) when multiple output drivers turn on and charge their load capacitances at the same time.
FIG. 7 shows a circuit diagram which illustrates a portion of an output circuit 700. As shown in FIG. 7, output circuit 700 is similar to output circuit 500 and, as a result, utilizes the same reference numerals to designate the structures which are common to both circuits.
As further shown in FIG. 7, output drivers driver#1-driver#N are each connected to a common VCC line 710. During normal operation, when a single output driver switches from a logic low to a logic high, a time varying charge current i(t)c is placed on VCC line 710. Similarly, when each of the output drivers driver#1-driver#N simultaneously switches from a logic low to a logic high, a large time varying current is placed on VCC line 710.
The large time varying current, which is the sum of the individual time varying charge currents i(t)c, causes the voltage on VCC line 710 to also vary due to the inductance of VCC line 710 (shown as inductor L). As shown by EQ. 4, the voltage variation VLV on VCC line 710 is defined as follows:VLV=L*N(di(t)/dt)  EQ. 4where L represents the inductance of VCC wire 710 (including package inductance and bondwire inductance), N represents the number of drivers driver#1-driver#N which charge their load capacitance at the same time, and di(t)/dt represents the time varying charge current i(t)c.
Thus, as shown in FIG. 7, extremely high VCC bounce (switching noise) can be generated when several drivers driver#1-driver#N switch from a logic low to a logic high at the same time.
Clean VCC lines usually service the relatively quiet (low di/dt) internal standard cells and/or digital macro cells. Depending upon the analog signal levels involved, the clean VCC lines may or may not be connected to the VCC lines which service the analog blocks.
In order to minimize crosstalk between the clean and dirty VCC lines, these lines must be isolated from each other. Generally speaking, analog VCC lines should be isolated from the dirty/clean VCC lines, and sensitive analog VCC lines are usually isolated from each other. None of this is possible in the prior art because, as shown in FIG. 3, the cathode of diode D1 is connected to a common VCC line.
4.5 Reliability Issues with Respect to Thin Oxide
Yet another disadvantage of using large p-channel and n-channel MOS transistors to make ESD diodes, such as transistors M1 and M2 in FIG. 3, is that these transistors contain thin gate oxide. As a result, these transistors are much more prone to ESD damage in comparison to ESD diodes which do not contain any thin oxide.
4.6 Summary of Disadvantages of the Prior Art
From the foregoing discussion, it can be seen that the main disadvantages of the prior ESD art (as illustrated in FIG. 3) can be summarized as follows:                ESD protection of multiple isolated VCC lines and multiple isolated ground lines is not possible.        The method of forming ESD protection diodes, utilizing parasitic bipolar transistors, imposes the following disadvantages:                    High forward voltage drop due to low beta and high equivalent base resistance            High leakage current due to large transistor size            High pin capacitance (especially bad for switchable high-impedance TRI-STATE™ outputs)            Low reliability (due to the presence of thin oxide in the ESD protection devices M1 and M2 in FIG. 3)            Common anode for all of the lower ESD protection diodes (as illustrated by diode D2 in FIG. 3)            Increased silicon area due to the large device sizes which are required                        
As implied by the above disadvantages, there is a great need for a more efficient ESD clamp diode, and a more flexible ESD clamping circuit. These items will now be discussed in the following paragraphs.